A signal generation apparatus that includes a PLL circuit configured using a voltage-controlled oscillator has been used in electronic devices that perform wireless communication. The oscillation frequency of the voltage-controlled oscillator is controlled by the PLL circuit so as to match the carrier frequency of the wireless communication channel that is to be used or the corresponding local oscillation frequency. Also, the oscillation signal generated by the voltage-controlled oscillator can be subjected to frequency modulation by changing the control voltage applied to the voltage-controlled oscillator.
However, since the oscillation frequency of the voltage-controlled oscillator fluctuates doe to process variations and temperature variations, there are cases where the oscillation frequency needs to be adjusted (calibrated). For example, in order to adjust the oscillation frequency, multiple capacitors included in a capacitor array are selectively connected to the voltage-controlled oscillator using multiple transistors for switching.
As an example of related technology, Patent Literature 1 discloses a voltage-controlled oscillator that includes: an inductor section and a varactor section that are connected between two nodes; a negative Gm section that is configured by two inverters that are parallel-connected in two directions between the two nodes, and a trimming capacitor array and a bias circuit that are connected to the respective nodes. By giving a bias voltage to the drain of the transistors for cutting off the capacitors, the bias circuit prevents a parasitic diode from switching on, thus making it possible to suppress an increase in phase noise. Here, the bias voltage is set so as to be higher to an the amplification voltage of the negative Gm section.
Also, Patent Literature 2 discloses a semiconductor integrated circuit that is directed to reducing the chip occupancy area as well as reducing fluctuation in the control gain of a digitally-controlled oscillator (DCO). This digitally-controlled oscillator includes an oscillation transistor and a resonance circuit. The resonance circuit includes an inductance, a variable capacity array for coarse frequency adjustment, and a variable capacity array for fine frequency adjustment. The variable capacity array for coarse frequency adjustment includes multiple coarse adjustment capacitor unit cells that are controlled by a coarse adjustment digital control signal having a predetermined number of bits. The variable capacity array for fine frequency adjustment includes multiple fine adjustment capacitor unit cells that are controlled by a fine adjustment digital control signal having a predetermined number of bits. The capacitance values of the coarse adjustment capacitor unit cells and the fine adjustment capacitor unit cells are set according to their respective binary weights.
When the transistors for selectively connecting the capacitors included in the capacitor array to the voltage-controlled oscillator are in the off state, if the voltage between the drain and the semiconductor substrate or the well changes, the parasitic capacitance between the drain and the reference potential (alternating ground potential) changes, and therefore the capacitance applied to the voltage-controlled oscillator changes.
Even if the capacitance applied to the voltage-controlled oscillator changes, as long as the PLL circuit is operating, the control voltage changes so as to absorb the change in capacitance, and thus the oscillation frequency of the voltage-controlled oscillator does not change. However, if the oscillation signal generated by the voltage-controlled oscillator is subjected to frequency modulation after the control loop of the PLL circuit has been cut off, drift will occur in the carrier frequency.